Staff ASIC Verification Engineers
SanDisk Corporation needs Staff ASIC Verification Engineers in Milpitas, California to be responsible for designing and developing a verification environment including test bench, test suites, and test vectors (UVM/OVM). Support current BICS2 and similar projects in term of debugging failures and becoming familiar with the SVA (System Verilog Assertion) for the BICS2. Responsible for generating and executing test plans in a constrained-random environment. Work with RTL, synthesis, and gate-level/SDF simulation. Execute coverage based verification plans and write functional coverage for complex ASICs. Responsible for scripting languages (TCL, Perl, Make, and Python), integration of different components for the Test bench, and verify and debug third party components. Identify issues in VIPs and solve issues which arise from the integration of components developed in different languages (C, C++, and System Verilog). Work with members of the UVM team covering 1A project. Coordinating execution and transition of the UVM and SVA verification standardized development flow for current and future projects with local and India teams. Detecting, filing (reporting), tracking and composing progress report on bugs detected in both Gate and RTL domains simulation.
Employer will accept Masters degree in Electrical Engineering or related technical field and 6 years of work experience in job offered or 6 years of work experience in a Verification Engineer or design engineer-related occupation. Experience must include:
1. 4 years of experience in Developing Testbench components like Drivers and Sequences for the Functional verification of complex Designs;
2. 4 years of experience in Generating and Executing coverage based verification plans based on design spec in a constrained-random verification environment, and, generating coverage models to achieve the Functional coverage goals;
3. 4 years of experience in Developing test cases to achieve maximum function coverage and be able to debug complex designs;
4. 2 years of experience in programming skills in object oriented programming, and UVM methodology;
5. NAND Memory;
6. Perl Scripting; and,
7. SVA( System Verilog Assertions).
Experience may be gained concurrently.
To apply, please reference job code #SD482 when mailing resume to:
SanDisk Corporation
951 SanDisk Drive
MS: HRGM
Milpitas, CA 95035Estimated Salary: $20 to $28 per hour based on qualifications.
Employer will accept Masters degree in Electrical Engineering or related technical field and 6 years of work experience in job offered or 6 years of work experience in a Verification Engineer or design engineer-related occupation. Experience must include:
1. 4 years of experience in Developing Testbench components like Drivers and Sequences for the Functional verification of complex Designs;
2. 4 years of experience in Generating and Executing coverage based verification plans based on design spec in a constrained-random verification environment, and, generating coverage models to achieve the Functional coverage goals;
3. 4 years of experience in Developing test cases to achieve maximum function coverage and be able to debug complex designs;
4. 2 years of experience in programming skills in object oriented programming, and UVM methodology;
5. NAND Memory;
6. Perl Scripting; and,
7. SVA( System Verilog Assertions).
Experience may be gained concurrently.
To apply, please reference job code #SD482 when mailing resume to:
SanDisk Corporation
951 SanDisk Drive
MS: HRGM
Milpitas, CA 95035Estimated Salary: $20 to $28 per hour based on qualifications.
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