PDG Full Chip Layout Verification DA CG 2014 Job - (folsom, california)
PDG Full Chip Layout Verification DA CG 2014 :
Description Come join Intels Product Development Group (PDG) as a Full Chip Layout Verification/Tapein DA.
In this position you will be developing, deploying, and supporting Section and Full:
chip Layout Verification tools and methodologies in support of cutting:
edge Client CPU projects within CMPG.
This includes:
:
Support for Section and Full:
chip Layout Verification flows and in the UE/PDS environment, including occasional cross:
site support :
Creating and delivering effective documentation and training on the current process node, will expert understanding of integration/tapein issues such as FC:
LVS, DRC, IP/NAC and Density IP flows :
Developing solutions to problems with a proactive attitude utilizing previous experience and judgment :
Applicants must be able to demonstrate clear written/documentation and oral communication skills :
They must be prepared to work with minimal supervision and maximum flexibility to meet project deadlines :
Strong problem:
solving skills :
Strong data analysis skills :
Strong written and verbal communication skills :
Attention to detail :
Customer orientation Qualifications Minimum
Qualifications:
:
Must be pursuing a BS or MS in Electrical Engineering, Computer Engineering, Computer Science or other science/engineering related field.
:
At the BS level only, must have the unrestricted right to work in the US without requiring sponsorship :
Minimum of 3 months experience with programming using Perl and/or UNIX shell Preferred
Qualifications:
:
Experience using CalibreDRV for either layout viewing/editing of runset verifications :
Experience with TCL/TK scripting/programming Job Category:
Engineering Full/Part Time:
Full Time Job Type:
College Graduate Regular/Temporary:
Regular Posting Date:
Jun 17, 2014 Apply Before :
Jun 28, 2014 Business Group The Platform Engineering Group (PEG) is responsible for the design, development, and production of system:
on:
a:
chip (SoC) products that go into Intel's next generation client and mobile platforms.
PEG strives to lead the industry moving forward through product innovation and world class engineering.
Source:
.
Estimated Salary: $20 to $28 per hour based on qualifications.
Description Come join Intels Product Development Group (PDG) as a Full Chip Layout Verification/Tapein DA.
In this position you will be developing, deploying, and supporting Section and Full:
chip Layout Verification tools and methodologies in support of cutting:
edge Client CPU projects within CMPG.
This includes:
:
Support for Section and Full:
chip Layout Verification flows and in the UE/PDS environment, including occasional cross:
site support :
Creating and delivering effective documentation and training on the current process node, will expert understanding of integration/tapein issues such as FC:
LVS, DRC, IP/NAC and Density IP flows :
Developing solutions to problems with a proactive attitude utilizing previous experience and judgment :
Applicants must be able to demonstrate clear written/documentation and oral communication skills :
They must be prepared to work with minimal supervision and maximum flexibility to meet project deadlines :
Strong problem:
solving skills :
Strong data analysis skills :
Strong written and verbal communication skills :
Attention to detail :
Customer orientation Qualifications Minimum
Qualifications:
:
Must be pursuing a BS or MS in Electrical Engineering, Computer Engineering, Computer Science or other science/engineering related field.
:
At the BS level only, must have the unrestricted right to work in the US without requiring sponsorship :
Minimum of 3 months experience with programming using Perl and/or UNIX shell Preferred
Qualifications:
:
Experience using CalibreDRV for either layout viewing/editing of runset verifications :
Experience with TCL/TK scripting/programming Job Category:
Engineering Full/Part Time:
Full Time Job Type:
College Graduate Regular/Temporary:
Regular Posting Date:
Jun 17, 2014 Apply Before :
Jun 28, 2014 Business Group The Platform Engineering Group (PEG) is responsible for the design, development, and production of system:
on:
a:
chip (SoC) products that go into Intel's next generation client and mobile platforms.
PEG strives to lead the industry moving forward through product innovation and world class engineering.
Source:
.
Estimated Salary: $20 to $28 per hour based on qualifications.
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